--
-- VHDL
--
-- Entity:	CLK4800
--	Purpose:	Given our 9.2416MHz/8 system clock, output the clocks
--				needed for 4800Baud.
--
--	Inputs:	CLK is the 9.2416/8 MHz clock which drives the process
--
--	Outputs:	clk4800 is about 4800HZ clock with 50% duty cycle.
--

library synth;
use synth.stdsynth.ALL;

entity CLK4800 is
  port (
	 signal clk      : in   vlbit;
	 signal clk4800  : out  vlbit);
end CLK4800;


architecture first of CLK4800 is

signal baudclk : vlbit := '0';
signal cnt     : vlbit_1d (7 downto 0) := "00000000";

begin
	-- Hardwire this flip-flop to the outgoiing port signal..
	clk4800 <= baudclk;

	DivideIt: process (clk)
	begin
		if Prising(clk) then

			-- To get a 4800 baud clk, first create a 9600 (twice the freq.) clk.
			--
			-- (9241600/8)/9600 = 120
			--
			if v1d2int(cnt) = 120 then
				-- One more Divide by 2 which also provides 50% duty cycle.
				baudclk <= NOT baudclk;
				cnt <= "00000000";
			else
				cnt <=  addum (cnt(6 downto 0), "1");
			end if;
		end if;
	end process DivideIt;
end first;