--
-- VHDL
--
-- MULTIPLIER:  Clocked Parallel, 4-bit inputs, 8-bit output
--              N clocks, where N equals 4
--
library synth;
use synth.stdsynth.ALL;

entity MULTA4 is
  port (
	 EN      : in  vlbit;
	 CLK     : in  vlbit;
	 A			: in  vlbit_1d(3 downto 0);
	 B  		: in  vlbit_1d(3 downto 0);
	 Q			: inout vlbit_1d(7 downto 0));
end MULTA4;


architecture first of MULTA4 is

signal B0MASK : vlbit_1d(6 downto 0);
signal B1MASK : vlbit_1d(6 downto 0);
signal B2MASK : vlbit_1d(6 downto 0);
signal B3MASK : vlbit_1d(6 downto 0);

signal CNT   : vlbit_1d(2 downto 0);

begin
	-- Expand the B bits into full vectors for our mask.
	-- Apparently, doing A AND B(2) wouldn't automatically
	-- expand the B bit to the appropriate size..
	--
	B0MASK <= "1111111" When B(0) = '1' Else
				 "0000000";
	B1MASK <= "1111111" When B(1) = '1' Else
				 "0000000";
	B2MASK <= "1111111" When B(2) = '1' Else
				 "0000000";
	B3MASK <= "1111111" When B(3) = '1' Else
				 "0000000";

	DoIt: Process (CLK)
	begin
		if CLK'EVENT AND CLK = '1' then
			if EN = '0' then
				CNT <= "000";
			else
				CNT <= addum (CNT(1 downto 0), "1");
				case v1d2int(CNT) is
					when 0 =>
						if B(0) = '1' then
							Q <= "0000" & A;
						else
							Q <= "00000000";
						end if;
					when 1 =>
						if B(1) = '1' then
							Q <= addum (Q(6 downto 0), "00" & A & "0");
						end if;
					when 2 =>
						if B(2) = '1' then
							Q <= addum (Q(6 downto 0), "0" & A & "00");
						end if;
					when 3 =>
						if B(3) = '1' then
							Q <= addum (Q(6 downto 0), A & "000");
						end if;
					when OTHERS => NULL;
				end case;
			end if;
		end if;
	end process;
end first;