--
-- VHDL
--
-- MULTIPLIER:  Fast Parallel, 4-bit inputs, 8-bit output
--
library synth;
use synth.stdsynth.ALL;

entity MULTB4 is
  port (
	 A			: in  vlbit_1d(3 downto 0);
	 B  		: in  vlbit_1d(3 downto 0);
	 Q			: out vlbit_1d(7 downto 0));
end MULTB4;


architecture first of MULTB4 is

signal B0MASK : vlbit_1d(6 downto 0);
signal B1MASK : vlbit_1d(6 downto 0);
signal B2MASK : vlbit_1d(6 downto 0);
signal B3MASK : vlbit_1d(6 downto 0);

signal LONGQ : vlbit_1d(8 downto 0);

begin
	-- Expand the B bits into full vectors for our mask.
	-- Apparently, doing A AND B(2) wouldn't automatically
	-- expand the B bit to the appropriate size..
	--
	B0MASK <= "1111111" When B(0) = '1' Else
				 "0000000";
	B1MASK <= "1111111" When B(1) = '1' Else
				 "0000000";
	B2MASK <= "1111111" When B(2) = '1' Else
				 "0000000";
	B3MASK <= "1111111" When B(3) = '1' Else
				 "0000000";

	-- Hmmm.. somehow we have an extra bit from all the adds...
	Q <= LONGQ(7 downto 0);

	-- This is it!
	LONGQ <= addum (addum ( ("000" & A)         AND B0MASK,
									("00"  & A & "0")   AND B1MASK),
						 addum ( ("0"   & A & "00" ) AND B2MASK,
									(        A & "000") AND B3MASK));
end first;